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| Semiconductor CD74HC393, CD74HCT393 High Speed CMOS Logic Dual 4 -Stage Binary Counter Description The Harris CD74HC393 and CD74HCT393 are 4-stage ripple-carry binary counters. Al counter stages are masterslave flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. September 1997 Features * Fully Static Operation * Buffered Inputs * Common Reset * Negative-Edge Clocking * Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF, TA = 25oC * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH Ordering Information PART NUMBER CD74HC393E CD74HCT393E CD74HC393M CD74HCT393M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld PDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC PKG. NO. E14.3 E14.3 M14.15 M14.15 Pinout CD74HC393, CD74HCT393 (PDIP, SOIC) TOP VIEW 1CP 1 1MR 2 1Q0 3 1Q1 4 1Q2 5 1Q3 6 GND 7 14 VCC 13 2CP 12 2MR 11 2Q0 10 2Q1 9 2Q2 8 2Q3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 File Number 1653.1 1 CD74HC393, CD74HCT393 Functional Diagram 3 1Q0 1 1CP 2 1MR BINARY COUNTER 4 1Q1 5 1Q2 6 1Q3 11 13 2CP 12 2MR BINARY COUNTER 10 9 8 2Q0 2Q1 2Q2 2Q3 GND = 7 VCC = 14 TRUTH TABLE OUTPUTS CP COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CP COUNT X Q0 L H L H L H L H L H L H L H L H MR L L H Q1 L L H H L L H H L L H H L L H H Q2 L L L L H H H H L L L L H H H H OUTPUT No Change Count LLLL Q3 L L L L L L L L H H H H H H H H NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High Level, = Transition from High to Low. 2 CD74HC393, CD74HCT393 Logic Diagram Q Q Q Q 1(13) CP R Q R Q R Q R Q 2(12) MR 3(11) Q0 Q1 4(10) Q2 5(9) Q3 6(8) 3 CD74HC393, CD74HCT393 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA Thermal Information Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS 4 CD74HC393, CD74HCT393 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS VCC (V) -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 0 0 - 5.5 5.5 4.5 to 5.5 - 100 0.1 8 360 - 1 80 450 - 1 160 490 A A A NOTE: For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT nCP nMR UNIT LOADS 0.4 1 NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360A max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER HC TYPES Maximum Clock Frequency fMAX 2 4.5 6 Clock Pulse Width tW 2 4.5 6 Reset Recovery Time tREC 2 4.5 6 6 30 35 80 16 14 5 5 5 5 24 28 100 20 17 5 5 5 4 20 24 120 24 20 5 5 5 ns ns ns ns ns ns ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS 5 CD74HC393, CD74HCT393 Prerequisite for Switching Specifications PARAMETER Reset Pulse Width SYMBOL tW VCC (V) 2 4.5 6 HCT TYPES Maximum Clock Frequency Clock Pulse Width Reset Recovery Time Reset Pulse Width fMAX tW tREC tW 4.5 4.5 4.5 4.5 27 19 5 16 22 24 5 20 18 29 5 24 MHz ns ns ns (Continued) 25oC MIN 80 16 14 TYP MAX -40oC TO 85oC MIN 100 20 17 MAX -55oC TO 125oC MIN 120 24 20 MAX UNITS ns ns ns Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay Time (Figure 1) Qn to Qn + 1 CL =15pF CL = 50pF nCP to nQ0 tPLH, tPHL CL = 50pF TEST SYMBOL CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 4.5 5 6 2 4.5 - 4 12 - 45 9 8 150 30 26 190 38 33 240 48 41 285 57 48 135 27 23 75 15 13 10 - - 55 11 9 190 38 33 245 49 42 300 60 51 355 71 60 170 34 29 95 19 16 10 - - 70 14 12 225 59 50 295 59 50 360 72 61 430 86 73 205 41 35 110 22 19 10 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF CL =15pF CL = 50pF nCP to nQ1 tPLH, tPHL CL = 50pF 5 6 2 4.5 6 nCP to nQ2 tPLH, tPHL CL = 50pF 2 4.5 6 nCP to nQ3 tPLH, tPHL CL = 50pF 2 4.5 6 - 11 20 MR to Qn tPLH, tPHL CL = 50pF 2 4.5 CL =15pF CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 5 6 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 4, 5) CIN CPD CL = 50pF CL =15pF 5 6 CD74HC393, CD74HCT393 Switching Specifications Input tr, tf = 6ns PARAMETER HCT TYPES Propagation Delay Time (Figure 1) Qn to Qn + 1 nCP to nQ0 tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL (Continued) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS TEST SYMBOL CONDITIONS tPLH, tPHL CL = 50pF CL =15pF CL = 50pF CL =15pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL =15pF 4.5 5 4.5 5 4.5 4.5 4.5 4.5 5 4.5 5 - 4 13 13 21 12 32 44 50 62 32 15 10 - - 15 40 55 63 78 40 19 10 - - 18 48 66 75 93 48 22 10 - ns ns ns ns ns ns ns ns ns ns pF pF nCP to nQ1 nCP to nQ2 nCP to nQ3 MR to Qn Output Transition Input Capacitance Power Dissipation Capacitance (Notes 4, 5) NOTES: tTLH, tTHL CL = 50pF CIN CPD CL =15pF CL =15pF 4. CPD is used to determine the dynamic power consumption, per stage. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tf = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% 3V tr = 6ns INPUT 90% 50% 10% tf = 6ns VCC tr = 6ns INPUT GND GND tTHL tTLH 90% 50% 10% tPHL tPLH tTHL INVERTING OUTPUT FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 7 |
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